march 1996 nds355n n-channel logic level enhancement mode field effect transistor general description features _______________________________________________________________________________ absolute maximum ratings t a = 25c unless otherwise noted symbol parameter nds355n units v dss drain-source voltage 30 v v gss gate-source voltage - continuous 20 v i d drain current - continuous (note 1a) 1.6 a - pulsed 10 p d maximum power dissipation (note 1a) 0.5 w (note 1b) 0.46 t j ,t stg operating and storage temperature range -55 to 150 c thermal characteristics r q ja thermal resistance, junction-to-ambient (note 1a) 250 c/w r q jc thermal resistance, junction-to -case (note 1) 75 c/w nds355n rev. d1 these n -c hannel logic level enhancement mode power field effect transistors are produced using fairchild's proprietary, high cell density, dmos technology. this very high density process is especially tailored to minimize on-state resistance. these devices are particularly suited for low voltage applications in notebook computers, portable phones, pcmica cards, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package. 1.6 a, 30v. ?r ds(on ) = 0.125 w @ v gs = 4.5v. proprietary package design using copper lead frame for superior thermal and electrical capabilities. high density cell design for extremely low r ds(on) . exceptional on-resistance and maximum dc current capability. compact industry standard sot-23 surface mount package. d s g ? 1997 fairchild semiconductor corporation
electrical characteristics (t a = 25c unless otherwise noted) symbol parameter conditions min typ max units off characteristics bv dss drain-source breakdown voltage v gs = 0 v, i d = 250 a 30 v i dss zero gate voltage drain current v ds = 24 v, v gs = 0 v 1 a t j =125c 10 a i gssf gate - body leakage, forward v gs = 12 v, v ds = 0 v 100 na i gssr gate - body leakage, reverse v gs = -12 v, v ds = 0 v -100 na on characteristics ( note 2 ) v gs (th) gate threshold voltage v ds = v gs , i d = 250 a 1 1.6 2 v t j =125c 0.5 1.3 1.5 r ds(on) static drain-source on-resistance v gs = 4.5 v, i d = 1.6 a 0.125 w t j =125c 0.25 v gs = 10 v, i d = 1.9 a 0.085 i d(on) on-state drain current v gs = 4.5 v, v ds = 5 v 6 a g fs forward transconductance v ds = 5 v, i d = 1.6 a 3.5 s dynamic characteristics c iss input capacitance v ds = 10 v, v gs = 0 v, f = 1.0 mhz 245 pf c oss output capacitance 130 pf c rss reverse transfer capacitance 20 pf switching ch aracteristics ( note 2 ) t d(on ) turn - on delay time v dd = 10 v, i d = 1 a, v gs = 10 v, r gen = 6 w 15 30 ns t r turn - on rise time 14 30 ns t d(off) turn - off delay time 12 25 ns t f turn - off fall time 4 10 ns q g total gate charge v ds = 10 v, i d = 1.6 a, v gs = 5 v 3.5 5 nc q gs gate-source charge 1 nc q gd gate-drain charge 2 nc nds355n rev. d1
electrical characteristics (t a = 25c unless otherwise noted) symbol parameter conditions min typ max units drain-source diode characteristics and maximum ratings i s maximum continuous source current 0.6 a i sm maximum pulse source current (note 2) 6 a v sd drain-source diode forward voltage v gs = 0 v, i s = 1.6 a 0.8 1.2 v notes: 1 . r q ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the so lder mounting surface of the drain pins. r q jc is guaranteed by design while r q ca is determined by the user's board design. p d ( t ) = t j - t a r q j a ( t ) = t j - t a r q j c + r q c a ( t ) = i d 2 ( t ) r d s ( o n ) t j typical r q ja using the board layouts shown below on 4.5"x5" fr-4 pcb in a still air environment : a. 250 o c/w when mounted on a 0.02 in 2 pad of 2oz cpper. b. 270 o c/w when mounted on a 0.001 in 2 pad of 2oz cpper. scale 1 : 1 on letter size paper 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. nds355n rev. d1 1a 1b
nds355n rev. d1 typical electrical characteristics figure 1. on-region characteristics figure 2. on-resistance variation wit h gate voltage and drain current 0 1 2 3 4 0 3 6 9 12 v , drain-source voltage (v) i , drain-source current (a) 6.0 5.0 4.5 4.0 3.5 3.0 v =10v gs ds d 0 3 6 9 12 0.5 1 1.5 2 i , drain current (a) drain-source on-resistance d r , normalized ds(on) 6.0 5.0 4.5 4.0 10 v =3.5v gs -50 -25 0 25 50 75 100 125 150 0.6 0.8 1 1.2 1.4 1.6 t , junction temperature (c) drain-source on-resistance j v =4.5v gs i = 1.6a d r , normalized ds(on) -50 -25 0 25 50 75 100 125 150 0.6 0.7 0.8 0.9 1 1.1 1.2 t , junction temperature (c) gate-source threshold voltage (v) j v , normalized th v = v ds gs i = 250a d 0 2 4 6 8 10 12 0.5 1 1.5 2 2.5 3 i , drain current (a) drain-source on-resistance t = 125c j 25c -55c d v = 4.5v gs r , normalized ds(on) figure 3. on-resistance variation with temperature figure 4. on-resistance variation with drain current and temperature figure 5. transfer characteristics figure 6. gate threshold variation with temperature 1 2 3 4 5 6 0 2 4 6 8 10 v , gate to source voltage (v) i , drain current (a) v = 10v ds gs d t = -55c j 25c 125c
nds355n rev. d1 -50 -25 0 25 50 75 100 125 150 175 0.9 0.95 1 1.05 1.1 1.15 t , junction temperature (c) drain-source breakdown voltage (v) i = 250a d bv , normalized dss j 0.2 0.4 0.6 0.8 1 1.2 1.4 0.001 0.01 0.1 1 10 20 v , body diode forward voltage (v) i , reverse drain current (a) v = 0v gs sd s t = 125c j 25c -55c 0 1 2 3 4 5 6 7 0 2 4 6 8 10 q , gate charge (nc) v , gate-source voltage (v) v = 5v ds g gs 10 i = 1.6a d 15 0.1 0.2 0.5 1 2 5 10 30 30 50 100 200 300 500 v , drain to source voltage (v) capacitance (pf) ds c iss c oss c rss f = 1 mhz v = 0v gs g d s v dd r l v v in out v gs dut r gen 10% 50% 90% 10% 90% 90% 50% input, v in output, v out t on t off t d(off) t f t r t d(on) inverted 10% pulse width figure 7. breakdown voltage variation with temperature figure 8. body diode forward voltage variation with current and temperature figure 9. capacitance characteristics figure 10. gate charge characteristics figure 11. switching test circuit figure 12. switching waveforms typical electrical characteristics (continued)
nds355n rev. d1 0 2 4 6 8 10 12 0 2 4 6 8 i , drain current (a) g , transconductance (siemens) d fs v = 5v ds t = 125c j 25c -55c d 0.1 1 2 5 10 20 30 50 0.01 0.1 0.5 1 2 10 20 v , drain-source voltage (v) i , drain current (a) d v = 10v single pulse t = 25c a rds(on) limit dc gs ds 1s 100ms 10s 10ms 1ms 100us figure 13. transconductance variation with drain current and temperature figure 14. maximum safe operating area typical electrical characteristics (continued) 0.0001 0.001 0.01 0.1 1 10 100 300 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 t , time (sec) transient thermal resistance r(t), normalized effective 1 single pulse d = 0.5 0.1 0.05 0.02 0.01 0.2 duty cycle, d = t /t 1 2 r (t) = r(t) * r r = 250 c/w q ja q ja q ja t - t = p * r (t) q ja a j p(pk) t 1 t 2 figure 15. transient thermal response curve note : characterization performed using the conditions described in note 1c. transient thermal response will change depending on the circuit board design .
disclaimer fairchild semiconductor reserves the right to make changes without further notice t o any products herein t o improve reliability , function or design. fairchild does not assume any liability arising out of the applica tion or use of any product or circuit described herein; neither does it convey any license under its p a tent rights, nor the rights of others. trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production optologic? optoplanar? pacman? pop? power247? powertrench qfet? qs? qt optoelectronics? quiet series? silent switcher fast fastr? frfet? globaloptoisolator? gto? hisec? isoplanar? littlefet? microfet? micropak? microwire? rev. h4 a acex? bottomless? coolfet? crossvolt ? densetrench? dome? ecospark? e 2 cmos tm ensigna tm fact? fact quiet series? smart start? star*power? stealth? supersot?-3 supersot?-6 supersot?-8 syncfet? tinylogic? trutranslation? uhc? ultrafet a a a star*power is used under license vcx?
|
